About the RIGOLETTO Automotive RISC-V Project

Collection of requirements with emphasis on the automotive domain, but including other relevant domains. We explicitly include industrial, robotics and health domains. Specifications for the designs and developments are also elaborated.

This work package will collect the requirements and specifications of the different hardware components of the platform, namely (i) scalable RISC-V automotive control processors, (ii) high-performance RISC-V based application processors, (iii) AI and ML accelerators, and (iv) the overall computing platform where the other components are integrated. For that purpose, use cases from the automotive domain, but also from industrial, robotics and health domains, will be leveraged to tailor the high-level requirements that the different hardware components must fulfil. Those will be further detailed with lower-level requirements related to implementation constraints, such as ISA extensions for the cores, data and operation types supported by the accelerators, and safety and security features needed at platform level, to name a few. From those requirements, specifications will be delivered for the different components. Particular care will be put on the different uses of those specifications (e.g., application development, hardware implementation, etc.) so that they are provided in the appropriate format for those purposes.

Design alternatives and configurations are explored in this WP, assessing tradeoffs and gaining knowledge to tailor developments in WP3 and WP4. This WP also includes the development and tailoring of tools such as simulators, compilers, etc. needed for the design of the technologies, as well as for their use.

This work package will perform architectural explorations and concept assessments for the different hardware components of the platform, namely (i) scalable RISC-V automotive control processors, (ii) high-performance RISC-V based application processors, (iii) AI and ML accelerators, and (iv) the overall computing platform where the other components are integrated. Moreover, this work package will also include the development of tools supporting the overall platform design process. In particular, architectural explorations and concept assessment will be used to identify the best designs and configurations for the different components and their integration thereof so that onerous implementations using low-level languages (e.g., RTL, VHDL, etc.) are only performed for those designs and configurations for which there is high confidence on their effectiveness. Regarding tools, they support a wide variety of processes from processor design, to verification, to performance validation, as well as runtime monitoring capabilities during operation

This WP includes the implementation, prototyping and modelling of the different IPs as standalone components. Interfaces are taken into account in those implementations, but integrations are left for WP4

This work package will perform the implementation of IP-blocks, virtual prototypes, and simulation models at the component level for the (i) scalable RISC-V automotive control processors, (ii) high-performance RISC-V based application processors, and (iii) AI and ML accelerators. The virtual prototypes and simulation models for the IP blocks will be carefully selected and planned, which will facilitate and expedite parallel implementation and validation. IP blocks, virtual prototypes, and simulation models will be implemented in respective languages (e.g., RTL/VHDL, SystemC, etc). The implementation will comply with the developed specifications, and for specific IPs, it will reflect the explored novel architectural concepts. A formal verification plan will be drawn, and formal verification methodologies will be optimized to provide (open-source) industrial-grade (high TRL) RISC-V IPs with near complete code coverage (~100%).

All developments related to integration occur in this WP. IPs are integrated, organized, and adapted as needed to make interfaces fully match. Integrations consider single SoC and multi-chiplet alternatives, as well as considerations related to physical design and testing so that the main roadblocks towards fabrication of the resulting integrations are removed.

This work package will comprise the integration of the IP-blocks and simulation models at the system level for the (i) scalable RISC-V automotive control processors, (ii) high performance RISC-V based applications processors and (iii) AI and ML accelerators. To provide a suitable conceptual framework for this integration, this work package will instance a number of reference architectures comprising (i), (ii) and (iii) above. In these reference architectures, more sophisticated memory hierarchies capable of exploiting temporal re-use of data to mitigate against memory bandwidth limits will be implemented. This work will be supported with the definition of high bandwidth memory controllers and interconnects, including, but not limited to CHI.E, CHI.G and AXI for enhanced interoperability with standard peripheral components capable of supporting RISC-V. In addition, a specific reference architecture will be considered capable of supporting the UCIe interface, demonstrating the suitability of the RIGOLETTO program outputs for a chiplet implementation. This work package will also consider implementation support for automotive safety features – to ensure safe and secure operation of the system.

This WP focuses on the demonstration and validation of the different technologies, which includes specific tests and simulations of standalone IPs, partial integrations and full integrations; performance validation tests including performance and power stress tests; porting and evaluation of use cases, etc. Adaptation of software to be run is likely needed in all cases, and such work is carried out in this WP.

This work package will demonstrate and validate the main features of the automotive computing platform, as well as its main computing components, namely the scalable RISC-V automotive control processors, the high-performance RISC-V application processors, and the AI and ML accelerators. Appropriate FPGA test environments will be used to perform test campaigns that will allow assessing the requirements devised as part of WP1, which relate to performance, safety, security, power, and the like. Broadly, metrics such as average performance, performance variability, performance corners, and memory bandwidth will be evaluated, as well as relevant features related to interfaces, tracing and debug support, interrupt management, and configuration of the platform and its components.

This WP includes activities related to setting up the hardware/software ecosystem inside the project and, especially, beyond the project, making sure that different hardware technologies can be properly connected, and software development and integration is simple and viable. In this regard, this WP also works on securing supply chains that allow building chips based on RIGOLETTO technology, and create full software stacks atop relevant for the target domains of the project.

This work package will focus on developing and enabling the (i) RISC-V Automotive Ecosystem and defining and fostering the (ii) RISC-V Automotive Supply Chain. Firstly, regarding the RISC-V Automotive Ecosystem, the contribution is twofold: from one side, to provide support for existing key (open-source) RISC-V Automotive software tools (e.g., compilers, OSes, Hypervisors, Frameworks) to the developed RISC-V Automotive Control Processors, High- Performance RISC-V based Application Processors, and AI and ML Accelerators; from another side, to contribute for public hardware repositories maintained by key RISC-V organizations, associations, and groups, with the open-source IPs developed across the three primary (component-level) streams of work. Secondly, regarding the RISC-V Automotive Supply Chain, the contribution will be centered first around identifying and defining this global network of players that can work together to bring RISC-V-enabled vehicles to the market and then liaison with identified key players.

This WP focuses on impact, which includes exploitation and IP management of the technologies developed, standardization (from compliance with and influence on RISC-V specifications, to compliance with ISO 26262, and other safety and security standards), as well as dissemination and communication activities.

This work package develops the necessary commercial and licensing frameworks for the IP developed during the project, as well as specifying standard descriptors, data structures and archival mechanisms for the IP itself. The work package also seeks to harmonize the extensions developed for (i) control and (ii) applications processors as well as (iii) AI and ML accelerators with the RISC-V specifications, and implementation guidance. Finally, this work package captures the dissemination and communication of the RIGOLETTO program outputs.

This WP supports the full project with management activities aiming at allowing to reach all objectives timely and with the intended quality by means of progress monitoring, risk management, setting up appropriate management tools, monitoring the use of resources, and securing an internal communication flow and proper synchronization among WPs and partners.

The activities of this work package aim at the implementation of the project and meeting the contractual obligations towards the EC. This includes the overall technical, administrative, financial and legal coordination of the project and the accurate and timely reporting to the EC, as well as all communication towards the Chips JU. The consortium aimed to maximize the technical efforts and therefore kept this work package as lean as possible. Efforts to run the other work packages WP1 – WP7 and their tasks are considered to be technical efforts which are allocated to WP1 – WP7 therefore. All efforts for dissemination and exploitation are assigned to work package 7 because these activities are so closely interwoven with the activities on business models and IP. WP8 interacts closely with all other work packages to monitor and aggregate the status and risks on project level, ensure a smooth implementation and to ensure a timely, consistent reporting.